Command block management

ABSTRACT

Methods, systems, and devices for command block management are described. A memory device may receive a command (e.g., from a host device). The memory device may determine whether the command is defined by determining if the command is included within a set of defined commands. In the case that a received command is absent from the set of defined commands (e.g., the command is undefined), the memory device may block the command from being decoded for execution by the memory device. In some cases, the memory device may switch from a first operation mode to a second operation mode based on receiving an undefined command. The second operation mode may restrict an operation of the memory device, while the first mode may be less restrictive, in some cases. Additionally or alternatively, the memory device may indicate the undefined command to another device (e.g., the host device).

CROSS REFERENCE

The present application for patent is a continuation of U.S. patentapplication Ser. No. 16/579,153 by Boehm et al., entitled “COMMAND BLOCKMANAGEMENT,” filed Sep. 23, 2019, which claims priority to U.S.Provisional Patent Application No. 62/746,284 by Boehm et al., entitled“COMMAND BLOCK MANAGEMENT,” filed Oct. 16, 2018, each of which isassigned to the assignee hereof and each of which is expresslyincorporated by reference in its entirety herein.

BACKGROUND

The following relates generally to a system that includes at least onememory device and more specifically to command block management.

Memory devices are widely used to store information in variouselectronic devices such as computers, wireless communication devices,cameras, digital displays, and the like. Information is stored byprogramming different states of a memory device. For example, binarydevices most often store one of two states, often denoted by a logic 1or a logic 0. In other devices, more than two states may be stored. Toaccess the stored information, a component of the device may read, orsense, at least one stored state in the memory device. To storeinformation, a component of the device may write, or program, the statein the memory device.

Types of memory devices include magnetic hard disks, random accessmemory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronousdynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM),resistive RAM (RRAM), flash memory, phase change memory (PCM), andothers. Memory devices may be volatile or non-volatile. Non-volatilememory, e.g., FeRAM, may maintain their stored logic state for extendedperiods of time even in the absence of an external power source.Volatile memory devices, e.g., DRAM, SRAM, may lose their stored statewhen disconnected from an external power source. Dynamic memory devices,e.g., DRAM, SDRAM, may lose a stored state over time unless they areperiodically refreshed.

In some cases, a memory device (e.g., a DRAM device) may be configuredto recognize a set of commands corresponding to unique instructions(e.g., read, write, refresh). For example, if a memory device receives acommand, the memory device may execute the command according to theindicated instruction. Improving memory devices, generally, may includeincreasing memory cell density, increasing read/write speeds, increasingreliability, increasing data retention, reducing power consumption, orreducing manufacturing costs, among other metrics. Improving a memorydevice's operation based on received commands is desired.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example of a system that supports command blockmanagement as disclosed herein.

FIG. 2 illustrates an example of a memory sub-array that supportscommand block management as disclosed herein.

FIG. 3 illustrates an example of a system that supports command blockmanagement as disclosed herein.

FIGS. 4 through 7 illustrate process flows that support command blockmanagement as disclosed herein.

FIGS. 8 and 9 illustrate block diagrams for apparatuses that supportcommand block management as disclosed herein.

FIGS. 10 through 14 illustrate a method or methods that support memorycommand verification as disclosed herein.

DETAILED DESCRIPTION

Memory devices may operate under various conditions as part ofelectronic apparatuses such as personal computers, wirelesscommunication devices, servers, internet-of-things (IoT) devices,electronic components of automotive vehicles, and the like. In somecases, memory devices supporting applications for certainimplementations (e.g., automotive vehicles, in some cases withautonomous or semi-autonomous driving capabilities) may be subject toincreased reliability constraints. As such, memory devices (e.g., DRAM)for some applications may be expected to operate with a reliabilitysubject to relatively higher industry specifications (e.g., higherreliability constraints).

Some memory devices may be configured to recognize a set of definedcommands corresponding to unique instructions (e.g., read, write,refresh) or addresses (e.g., row address, column address). For example,if a memory device receives a defined command, the memory device mayexecute the command according to the indicated instruction and address.In some cases, there may be commands that are not defined for the memorydevice (e.g., commands that do not correspond to a defined instructionand/or defined address). That is, there may be commands or commandsequences that do not correspond to a defined operation or set ofoperations.

For example, commands may be conveyed by the states of pins of thememory device, and a subset of the possible combinations of the pins maynot correspond to defined operations for the memory device. In the casethat a memory device receives an undefined command or command sequence,the response of the memory device may be variable or unknown. Forexample, a memory device may not have a defined operation associatedwith an undefined command and as such, may execute variable operationsin response to the undefined command. In some cases, undefined commandsleading to variable operations may leave the memory device susceptibleto malicious attacks. That is, a command or series of commands may besent to the memory device in order to cause the memory device to behaveerratically.

Techniques for blocking undefined commands from execution at the memorydevice are described. For example, the memory device may determinewhether a command is defined prior to decoding and executing thecommand. The memory device may identify a set of defined commands forthe memory device. When the memory device receives a command or asequence of commands, the memory device may determine whether eachcommand of the received commands is defined by determining if eachreceived command is absent or present within the set of definedcommands. In the case that a received command is absent from the set ofdefined commands (e.g., the command is undefined), the memory device mayblock the command from being decoded for execution by the memory device.In one example, the memory device may activate a safe mode for thememory array associated with the detected undefined command. The safemode may restrict the operation of the memory device (e.g., by limitingthe type of commands executed, by limiting the portion of a memory arrayof the memory device for executing commands). Additionally oralternatively, the memory device may transmit a notification to a hostdevice indicating the undefined command. Thus, the memory device mayprevent the execution of undefined commands in order to improve thereliability of the memory device (e.g., by decreasing variable behaviorof the memory device).

Features of the disclosure are initially described in the context of amemory system and device with reference to FIGS. 1, 2, and 3 . Featuresof the disclosure are described in the context of a process flow withreference to FIGS. 4, 5, 6, and 7 . These and other features of thedisclosure are further illustrated by and described with reference toapparatus diagrams and flowcharts in FIGS. 8-14 that relate to commandblock management.

FIG. 1 illustrates an example of a system 100 that utilizes one or morememory devices in accordance with aspects disclosed herein. The system100 may include an external memory controller 105, a memory device 110,and a plurality of channels 115 coupling the external memory controller105 with the memory device 110. The system 100 may include one or morememory devices, but for ease of description the one or more memorydevices may be described as a single memory device 110.

The system 100 may include aspects of an electronic device, such as acomputing device, a mobile computing device, a wireless device, or agraphics processing device. The system 100 may be an example of aportable electronic device. The system 100 may be an example of acomputer, a laptop computer, a tablet computer, a smartphone, a cellularphone, a wearable device, an internet-connected device, or the like. Thememory device 110 may be component of the system configured to storedata for one or more other components of the system 100. In someexamples, the system 100 is configured for bi-directional wirelesscommunication with other systems or devices using a base station oraccess point. In some examples, the system 100 is capable ofmachine-type communication (MTC), machine-to-machine (M2M)communication, or device-to-device (D2D) communication.

At least portions of the system 100 may be examples of a host device.Such a host device may be an example of a device that uses memory toexecute processes such as a computing device, a mobile computing device,a wireless device, a graphics processing device, a computer, a laptopcomputer, a tablet computer, a smartphone, a cellular phone, a wearabledevice, an internet-connected device, some other stationary or portableelectronic device, or the like. In some examples, system 100 is agraphics card. In some cases, the host device may refer to the hardware,firmware, software, or a combination thereof that implements thefunctions of the external memory controller 105. In some cases, theexternal memory controller 105 may be referred to as a host or hostdevice.

In some cases, the memory device 110 may be an independent device orcomponent that is configured to be in communication with othercomponents of the system 100 and provide physical memory addresses/spaceto potentially be used or referenced by the system 100. In someexamples, a memory device 110 may be configurable to work with at leastone or a plurality of different types of systems 100. Signaling betweenthe components of the system 100 and the memory device 110 may beoperable to support modulation schemes to modulate the signals,different pin designs for communicating the signals, distinct packagingof the system 100 and the memory device 110, clock signaling andsynchronization between the system 100 and the memory device 110, timingconventions, and/or other factors.

The memory device 110 may be configured to store data for the componentsof the system 100. In some cases, the memory device 110 may act as aslave-type device to the system 100 (e.g., responding to and executingcommands provided by the system 100 through the external memorycontroller 105). Such commands may include an access command for anaccess operation, such as a write command for a write operation, a readcommand for a read operation, a refresh command for a refresh operation,or other commands. The memory device 110 may include two or more memorydice 160 (e.g., memory chips) to support a desired or specified capacityfor data storage. The memory device 110 including two or more memorydice may be referred to as a multi-die memory or package (also referredto as multi-chip memory or package).

The system 100 may further include a processor 120, a basic input/outputsystem (BIOS) component 125, one or more peripheral components 130, andan input/output (I/O) controller 135. The components of system 100 maybe in electronic communication with one another using a bus 140.

The processor 120 may be configured to control at least portions of thesystem 100. The processor 120 may be a general-purpose processor, adigital signal processor (DSP), an application-specific integratedcircuit (ASIC), a field-programmable gate array (FPGA) or otherprogrammable logic device, discrete gate or transistor logic, discretehardware components, or it may be a combination of these types ofcomponents. In such cases, the processor 120 may be an example of acentral processing unit (CPU), a graphics processing unit (GPU), ageneral purpose GPU (GPGPU), or a system on a chip (SoC), among otherexamples.

The BIOS component 125 may be a software component that includes a BIOSoperated as firmware, which may initialize and run various hardwarecomponents of the system 100. The BIOS component 125 may also managedata flow between the processor 120 and the various components of thesystem 100, e.g., the peripheral components 130, the I/O controller 135,etc. The BIOS component 125 may include a program or software stored inread-only memory (ROM), flash memory, or any other non-volatile memory.

The peripheral component(s) 130 may be any input device or outputdevice, or an interface for such devices, that may be integrated into orwith the system 100. Examples may include disk controllers, soundcontroller, graphics controller, Ethernet controller, modem, universalserial bus (USB) controller, a serial or parallel port, or peripheralcard slots, such as peripheral component interconnect (PCI) oraccelerated graphics port (AGP) slots. The peripheral component(s) 130may be other components understood by those skilled in the art asperipherals.

The I/O controller 135 may manage data communication between theprocessor 120 and the peripheral component(s) 130, input devices 145, oroutput devices 150. The I/O controller 135 may manage peripherals thatare not integrated into or with the system 100. In some cases, the I/Ocontroller 135 may represent a physical connection or port to externalperipheral components.

The input 145 may represent a device or signal external to the system100 that provides information, signals, or data to the system 100 or itscomponents. This may include a user interface or interface with orbetween other devices. In some cases, the input 145 may be a peripheralthat interfaces with system 100 via one or more peripheral components130 or may be managed by the I/O controller 135.

The output 150 may represent a device or signal external to the system100 configured to receive an output from the system 100 or any of itscomponents. Examples of the output 150 may include a display, audiospeakers, a printing device, or another processor on printed circuitboard, and so forth. In some cases, the output 150 may be a peripheralthat interfaces with the system 100 via one or more peripheralcomponents 130 or may be managed by the I/O controller 135.

The components of system 100 may be made up of general-purpose orspecial purpose circuitry designed to carry out their functions. Thismay include various circuit elements, for example, conductive lines,transistors, capacitors, inductors, resistors, amplifiers, or otheractive or passive elements, configured to carry out the functionsdescribed herein.

The memory device 110 may include a device memory controller 155 and oneor more memory dice 160. Each memory die 160 may include a local memorycontroller 165 (e.g., local memory controller 165-a, local memorycontroller 165-b, and/or local memory controller 165-N) and a memoryarray 170 (e.g., memory array 170-a, memory array 170-b, and/or memoryarray 170-N). A memory array 170 may be a collection (e.g., a grid) ofmemory cells, with each memory cell being configured to store at leastone bit of digital data. Features of memory arrays 170 and/or memorycells are described in more detail with reference to FIG. 2 .

The memory device 110 may be an example of a two-dimensional (2D) arrayof memory cells or may be an example of a three-dimensional (3D) arrayof memory cells. For example, a 2D memory device may include a singlememory die 160. A 3D memory device may include two or more memory dice160 (e.g., memory die 160-a, memory die 160-b, and/or any number ofmemory dice 160-N). In a 3D memory device, a plurality of memory dice160-N may be stacked on top of one another. In some cases, memory dice160-N in a 3D memory device may be referred to as decks, levels, layers,or dies. A 3D memory device may include any quantity of stacked memorydice 160-N (e.g., two high, three high, four high, five high, six high,seven high, eight high). This may increase the number of memory cellsthat may be positioned on a substrate as compared with a single 2Dmemory device, which in turn may reduce production costs or increase theperformance of the memory array, or both. In some 3D memory device,different decks may share at least one common access line such that somedecks may share at least one of a word line, a digit line, and/or aplate line.

The device memory controller 155 may include circuits or componentsconfigured to control operation of the memory device 110. As such, thedevice memory controller 155 may include the hardware, firmware, andsoftware that enables the memory device 110 to perform commands and maybe configured to receive, transmit, or execute commands, data, orcontrol information related to the memory device 110. The device memorycontroller 155 may be configured to communicate with the external memorycontroller 105, the one or more memory dice 160, or the processor 120.In some cases, the memory device 110 may receive data and/or commandsfrom the external memory controller 105. For example, the memory device110 may receive a write command indicating that the memory device 110 isto store certain data on behalf of a component of the system 100 (e.g.,the processor 120) or a read command indicating that the memory device110 is to provide certain data stored in a memory die 160 to a componentof the system 100 (e.g., the processor 120).

The memory device 110 may store a set of defined commands correspondingto unique instructions (e.g., read, write, refresh) or addresses (e.g.,row address, column address). In some cases, the memory device 110 maydetermine that a command (e.g., received from the external memorycontroller 105) is defined prior to executing the command at a memoryarray 170. Further, the memory device 110 may block undefined commands(e.g., commands that do not correspond to a defined instruction and/ordefined address) and by not decoding and/or executing undefinedcommands. In one example, the memory device 110 may activate a safe modefor a memory array 170 associated with the undefined command. The safemode may restrict the execution of commands at a certain portion of thememory array 170 (e.g., a bank or banks associated with the undefinedcommand). Additionally or alternatively, the safe mode may restrict thetype of commands for execution (e.g., the safe mode may allow anexecution of read commands while restricting an execution of writecommands). In some examples, the memory device 110 may transmit anotification to the external memory controller 105 related to theundefined command.

In some cases, the device memory controller 155 may control operation ofthe memory device 110 described herein in conjunction with the localmemory controller 165 of the memory die 160. Examples of the componentsincluded in the device memory controller 155 and/or the local memorycontrollers 165 may include receivers for demodulating signals receivedfrom the external memory controller 105, decoders for modulating andtransmitting signals to the external memory controller 105, logic,decoders, amplifiers, filters, or the like.

The local memory controller 165 (e.g., local to a memory die 160) may beconfigured to control operations of the memory die 160. Also, the localmemory controller 165 may be configured to communicate (e.g., receiveand transmit data and/or commands) with the device memory controller155. The local memory controller 165 may support the device memorycontroller 155 to control operation of the memory device 110 asdescribed herein. In some cases, the memory device 110 does not includethe device memory controller 155, and the local memory controller 165 orthe external memory controller 105 may perform the various functionsdescribed herein. As such, the local memory controller 165 may beconfigured to communicate with the device memory controller 155, withother local memory controllers 165, or directly with the external memorycontroller 105 or the processor 120.

The external memory controller 105 may be configured to enablecommunication of information, data, and/or commands between componentsof the system 100 (e.g., the processor 120) and the memory device 110.The external memory controller 105 may act as a liaison between thecomponents of the system 100 and the memory device 110 so that thecomponents of the system 100 may not need to know the details of thememory device's operation. The components of the system 100 may presentrequests to the external memory controller 105 (e.g., read commands orwrite commands) that the external memory controller 105 satisfies. Theexternal memory controller 105 may convert or translate communicationsexchanged between the components of the system 100 and the memory device110. In some cases, the external memory controller 105 may include asystem clock that generates a common (source) system clock signal. Insome cases, the external memory controller 105 may include a common dataclock that generates a common (source) data clock signal.

In some cases, the external memory controller 105 or other component ofthe system 100, or its functions described herein, may be implemented bythe processor 120. For example, the external memory controller 105 maybe hardware, firmware, or software, or some combination thereofimplemented by the processor 120 or other component of the system 100.While the external memory controller 105 is depicted as being externalto the memory device 110, in some cases, the external memory controller105, or its functions described herein, may be implemented by a memorydevice 110. For example, the external memory controller 105 may behardware, firmware, or software, or some combination thereof implementedby the device memory controller 155 or one or more local memorycontrollers 165. In some cases, the external memory controller 105 maybe distributed across the processor 120 and the memory device 110 suchthat portions of the external memory controller 105 are implemented bythe processor 120 and other portions are implemented by a device memorycontroller 155 or a local memory controller 165. Likewise, in somecases, one or more functions ascribed herein to the device memorycontroller 155 or local memory controller 165 may in some cases beperformed by the external memory controller 105 (either separate from oras included in the processor 120).

The components of the system 100 may exchange information with thememory device 110 using a plurality of channels 115. In some examples,the channels 115 may enable communications between the external memorycontroller 105 and the memory device 110. Each channel 115 may includeone or more signal paths or transmission mediums (e.g., conductors)between terminals associated with the components of system 100. Forexample, a channel 115 may include a first terminal including one ormore pins or pads at external memory controller 105 and one or more pinsor pads at the memory device 110. A pin may be an example of aconductive input or output point of a device of the system 100, and apin may be configured to act as part of a channel. In some cases, a pinor pad of a terminal may be part of to a signal path of the channel 115.Additional signal paths may be coupled with a terminal of a channel forrouting signals within a component of the system 100. For example, thememory device 110 may include signal paths (e.g., signal paths internalto the memory device 110 or its components, such as internal to a memorydie 160) that route a signal from a terminal of a channel 115 to thevarious components of the memory device 110 (e.g., a device memorycontroller 155, memory dice 160, local memory controllers 165, memoryarrays 170).

Channels 115 (and associated signal paths and terminals) may bededicated to communicating specific types of information. In some cases,a channel 115 may be an aggregated channel and thus may include multipleindividual channels. For example, a data channel 190 may be ×4 (e.g.,including four signal paths), ×8 (e.g., including eight signal paths),×16 (including sixteen signal paths), and so forth.

In some cases, the channels 115 may include one or more command andaddress (CA) channels 186. The CA channels 186 may be configured tocommunicate commands between the external memory controller 105 and thememory device 110 including control information associated with thecommands (e.g., address information). For example, the CA channel 186may include a read command with an address of the desired data. In somecases, the CA channels 186 may be registered on a rising clock signaledge and/or a falling clock signal edge. In some cases, a CA channel 186may include eight or nine signal paths.

In some cases, the channels 115 may include one or more clock signal(CK) channels 188. The CK channels 188 may be configured to communicateone or more common clock signals between the external memory controller105 and the memory device 110. Each clock signal may be configured tooscillate between a high state and a low state and coordinate theactions of the external memory controller 105 and the memory device 110.In some cases, the clock signal may be a differential output (e.g., aCK_t signal and a CK_c signal) and the signal paths of the CK channels188 may be configured accordingly. In some cases, the clock signal maybe single ended. In some cases, the clock signal may be a 1.5 GHzsignal. A CK channel 188 may include any number of signal paths. In somecases, the clock signal CK (e.g., a CK_t signal and a CK_c signal) mayprovide a timing reference for command and addressing operations for thememory device 110, or other system-wide operations for the memory device110. The clock signal CK therefore may be variously referred to as acontrol clock signal CK, a command clock signal CK, or a system clocksignal CK. The system clock signal CK may be generated by a systemclock, which may include one or more hardware components (e.g.,oscillators, crystals, logic gates, transistors, or the like).

In some cases, the channels 115 may include one or more data (DQ)channels 190. The data channels 190 may be configured to communicatedata and/or control information between the external memory controller105 and the memory device 110. For example, the data channels 190 maycommunicate information (e.g., bi-directional) to be written to thememory device 110 or information read from the memory device 110. Thedata channels 190 may communicate signals that may be modulated using avariety of different modulation schemes (e.g., NRZ, PAM4).

In some cases, the channels 115 may include one or more other channels192 that may be dedicated to other purposes. These other channels 192may include any number of signal paths.

In some cases, the other channels 192 may include one or more writeclock signal (WCK) channels. While the ‘W’ in WCK may nominally standfor “write,” a write clock signal WCK (e.g., a WCK_t signal and a WCK_csignal) may provide a timing reference for access operations generallyfor the memory device 110 (e.g., a timing reference for both read andwrite operations). Accordingly, the write clock signal WCK may also bereferred to as a data clock signal WCK. The WCK channels may beconfigured to communicate a common data clock signal between theexternal memory controller 105 and the memory device 110. The data clocksignal may be configured to coordinate an access operation (e.g., awrite operation or read operation) of the external memory controller 105and the memory device 110. In some cases, the write clock signal may bea differential output (e.g., a WCK_t signal and a WCK_c signal) and thesignal paths of the WCK channels may be configured accordingly. A WCKchannel may include any number of signal paths. The data clock signalWCK may be generated by a data clock, which may include one or morehardware components (e.g., oscillators, crystals, logic gates,transistors, or the like).

In some cases, the other channels 192 may include one or more errordetection code (EDC) channels. The EDC channels may be configured tocommunicate error detection signals, such as checksums, to improvesystem reliability. An EDC channel may include any number of signalpaths.

The channels 115 may couple the external memory controller 105 with thememory device 110 using a variety of different architectures. Examplesof the various architectures may include a bus, a point-to-pointconnection, a crossbar, a high-density interposer such as a siliconinterposer, or channels formed in an organic substrate or somecombination thereof. For example, in some cases, the signal paths may atleast partially include a high-density interposer, such as a siliconinterposer or a glass interposer.

Signals communicated over the channels 115 may be modulated using avariety of different modulation schemes. In some cases, a binary-symbol(or binary-level) modulation scheme may be used to modulate signalscommunicated between the external memory controller 105 and the memorydevice 110. A binary-symbol modulation scheme may be an example of aM-ary modulation scheme where M is equal to two. Each symbol of abinary-symbol modulation scheme may be configured to represent one bitof digital data (e.g., a symbol may represent a logic 1 or a logic 0).Examples of binary-symbol modulation schemes include, but are notlimited to, non-return-to-zero (NRZ), unipolar encoding, bipolarencoding, Manchester encoding, pulse amplitude modulation (PAM) havingtwo symbols (e.g., PAM2), and/or others.

In some cases, a multi-symbol (or multi-level) modulation scheme may beused to modulate signals communicated between the external memorycontroller 105 and the memory device 110. A multi-symbol modulationscheme may be an example of a M-ary modulation scheme where M is greaterthan or equal to three. Each symbol of a multi-symbol modulation schememay be configured to represent more than one bit of digital data (e.g.,a symbol may represent a logic 00, a logic 01, a logic 10, or a logic11). Examples of multi-symbol modulation schemes include, but are notlimited to, PAM4, PAM8, etc., quadrature amplitude modulation (QAM),quadrature phase shift keying (QPSK), and/or others. A multi-symbolsignal or a PAM4 signal may be a signal that is modulated using amodulation scheme that includes at least three levels to encode morethan one bit of information. Multi-symbol modulation schemes and symbolsmay alternatively be referred to as non-binary, multi-bit, orhigher-order modulation schemes and symbols.

FIG. 2 illustrates an example of a memory sub-array 200 in accordancewith various examples of the present disclosure. The memory sub-array200 may be an example of at least a portion of the memory dice 160described with reference to FIG. 1 . In some cases, the memory sub-array200 may be referred to as a memory die, memory chip, a memory device, oran electronic memory apparatus. For example, a memory device such as amemory chip may include multiple instances of sub-array 200, withadditional row, address, bank, or bank group decoding used to select oneor more sub-arrays from the multiple instances for access operations.The memory sub-array 200 may include one or more memory cells 205 thatare programmable to store different logic states. Each memory cell 205may be programmable to store two or more states. For example, the memorycell 205 may be configured to store one bit of digital logic at a time(e.g., a logic 0 and a logic 1). In some cases, a single memory cell 205(e.g., a multi-level memory cell) may be configured to store more thanone bit of digit logic at a time (e.g., a logic 00, logic 01, logic 10,or a logic 11).

A memory cell 205 may store a charge representative of the programmablestates in a capacitor. DRAM architectures may include a capacitor thatincludes a dielectric material to store a charge representative of theprogrammable state. In other memory architectures, other storage devicesand components are possible. For example, nonlinear dielectric materialsmay be employed.

Operations such as reading and writing may be performed on memory cells205 by activating or selecting access lines such as a word line 210and/or a digit line 215. In some cases, digit lines 215 may also bereferred to as bit lines. References to access lines, word lines anddigit lines, or their analogues, are interchangeable without loss ofunderstanding or operation. Activating or selecting a word line 210 or adigit line 215 may include applying a voltage to the respective line orconfiguring a multiplexer to map the line to a given signal.

The memory sub-array 200 may include the access lines (e.g., the wordlines 210 and the digit lines 215) arranged in a grid-like pattern.Memory cells 205 may be positioned at intersections of the word lines210 and the digit lines 215. By biasing a word line 210 (e.g., applyinga voltage to the word line 210), a memory cell 205 may be accessed viathe digit line 215 at their intersection.

Accessing the memory cells 205 may be controlled through a row decoder220 or a column decoder 225. For example, a row decoder 220 may receivea row address from the local memory controller 260 and activate a wordline 210 based on the received row address. A column decoder 225 mayreceive a column address from the local memory controller 260 and mayselect a digit line 215 based on the received column address. Forexample, the memory sub-array 200 may include multiple word lines 210,labeled WL_1 through WL_M, and multiple digit lines 215, labeled DL_1through DL_N, where M and N depend on the size of the memory array.Thus, by activating a word line 210, e.g., WL_1, the memory cells 205 ina given row may be accessed. The digit lines 215 (e.g., DL_1, . . . ,DL_N) carry the data for writing or reading from the memory cells in therow. The intersection of a word line 210 and a digit line 215, in eithera two-dimensional or three-dimensional configuration, may be referred toas an address of a memory cell 205.

The memory cell 205 may include a logic storage component, such ascapacitor 230 and a switching component 235. The capacitor 230 may be anexample of a dielectric capacitor or a ferroelectric capacitor. A firstnode of the capacitor 230 may be coupled with the switching component235 and a second node of the capacitor 230 may be coupled with a voltagesource 240. In some cases, the voltage source 240 may be the cell platereference voltage, such as Vpl, or may be ground, such as Vss. In somecases, the voltage source 240 may be an example of a plate line coupledwith a plate line driver. The switching component 235 may be an exampleof a transistor or any other type of switch device that selectivelyestablishes or de-establishes electronic communication between twocomponents.

Selecting or deselecting the memory cell 205 may be accomplished byactivating or deactivating the switching component 235. The capacitor230 may be in electronic communication with the digit line 215 using theswitching component 235. For example, the capacitor 230 may be isolatedfrom digit line 215 when the switching component 235 is deactivated, andthe capacitor 230 may be coupled with digit line 215 when the switchingcomponent 235 is activated. In some cases, the switching component 235is a transistor and its operation may be controlled by applying avoltage to the transistor gate, where the voltage differential betweenthe transistor gate and transistor source may be greater or less than athreshold voltage of the transistor. In some cases, the switchingcomponent 235 may be a p-type transistor or an n-type transistor. Theword line 210 may be in electronic communication with the gate of theswitching component 235 and may activate/deactivate the switchingcomponent 235 based on a voltage being applied to word line 210.

A word line 210 may be a conductive line in electronic communicationwith a memory cell 205 that is used to perform access operations on thememory cell 205. In some architectures, the word line 210 may be inelectronic communication with a gate of a switching component 235 of amemory cell 205 and may be configured to control the switching component235 of the memory cell. In some architectures, the word line 210 may bein electronic communication with a node of the capacitor of the memorycell 205 and the memory cell 205 may not include a switching component.

A digit line 215 may be a conductive line that connects the memory cell205 with a sense component 245. In some architectures, the memory cell205 may be selectively coupled with the digit line 215 during portionsof an access operation. For example, the word line 210 and the switchingcomponent 235 of the memory cell 205 may be configured to couple and/orisolate the capacitor 230 of the memory cell 205 and the digit line 215.In some architectures, the memory cell 205 may be in electroniccommunication (e.g., constant) with the digit line 215.

The sense component 245 may be configured to detect a state (e.g., acharge) stored on the capacitor 230 of the memory cell 205 and determinea logic state of the memory cell 205 based on the stored state. Thecharge stored by a memory cell 205 may be extremely small, in somecases. As such, the sense component 245 may include one or more senseamplifiers to amplify the signal output by the memory cell 205. Thesense amplifiers may detect small changes in the charge of a digit line215 during a read operation and may produce signals corresponding to alogic state 0 or a logic state 1 based on the detected charge. During aread operation, the capacitor 230 of memory cell 205 may output a signal(e.g., via charge sharing) to its corresponding digit line 215. Thesignal may cause a voltage of the digit line 215 to change. The sensecomponent 245 may be configured to compare the signal received from thememory cell 205 across the digit line 215 to a reference signal 250(e.g., reference voltage). The sense component 245 may determine thestored state of the memory cell 205 based on the comparison. Forexample, in binary-signaling, if digit line 215 has a higher voltagethan the reference signal 250, the sense component 245 may determinethat the stored state of memory cell 205 is a logic 1 and, if the digitline 215 has a lower voltage than the reference signal 250, the sensecomponent 245 may determine that the stored state of the memory cell 205is a logic 0. The sense component 245 may include amplifiers (e.g.,transistor amplifiers) to detect and amplify a difference in thesignals. The detected logic state of memory cell 205 may be outputthrough column decoder 225 as output 255. In some cases, the aspects ofsense component 245 may be part of another component (e.g., a columndecoder 225, row decoder 220). In some cases, the sense component 245may be in electronic communication with the row decoder 220 or thecolumn decoder 225.

The local memory controller 260 may control the operation of memorycells 205 through the various components (e.g., row decoder 220, columndecoder 225, and sense component 245). The local memory controller 260may be an example of the local memory controller 165 described withreference to FIG. 1 . In some cases, aspects of the row decoder 220,column decoder 225, or sense component 245 may be co-located with thelocal memory controller 260. The local memory controller 260 may beconfigured to receive commands and/or data from an external memorycontroller 105 (or a device memory controller 155 described withreference to FIG. 1 ) and translate the commands and/or data intoinformation that can be used by the memory sub-array 200.

The local memory controller 260 may determine whether received commandsare defined prior to translating the commands into information that canbe used by the memory sub-array 200. That is, the local memorycontroller 260 may compare received commands to a set of definedcommands. In the event that the received command is included in the setof defined commands, the local memory controller may translate thecommands into information that can be used by the memory sub-array 200.Alternatively, in the event that the received command is not included inthe set of defined commands (e.g., the received command isundefined/invalid), the local memory controller 260 may block thecommand from being translated and propagated to the memory sub-array200. In one example, the local memory controller 260 may activate a safemode for the memory sub-array 200 associated with the undefined command.The safe mode may restrict the execution of commands at a certainportion of the sub-array 200 (e.g., a bank or banks associated with theundefined command). Additionally or alternatively, the safe mode mayrestrict the type of commands for execution (e.g., the safe mode mayallow an execution of read commands while restricting an execution ofwrite commands). Further, the local memory controller 260 may transmit anotification a host device (e.g., an external memory controller 105 asdescribed with reference to FIG. 1 ) related to the undefined command.

The local memory controller 260 may further be configured to perform oneor more operations on the memory sub-array 200, and communicate datafrom the memory sub-array 200 to the external memory controller 105 (orthe device memory controller 155) in response to performing the one ormore operations. The local memory controller 260 may generate row andcolumn address signals to activate the target word line 210 and selectthe target digit line 215. The local memory controller 260 may alsogenerate and control various voltages or currents used during theoperation of the memory sub-array 200. In general, the amplitude, shape,or duration of an applied voltage or current discussed herein may beadjusted or varied and may be different for the various operationsdiscussed in operating the memory sub-array 200.

In some cases, the local memory controller 260 may be configured toperform a write operation (e.g., a programming operation) on one or morememory cells 205 of the memory sub-array 200. During a write operation,a memory cell 205 of the memory sub-array 200 may be programmed to storea desired logic state. In some cases, a plurality of memory cells 205may be programmed during a single write operation. The local memorycontroller 260 may identify a target memory cell 205 on which to performthe write operation. The local memory controller 260 may identify atarget word line 210 and a target digit line 215 in electroniccommunication with the target memory cell 205 (e.g., the address of thetarget memory cell 205). The local memory controller 260 may activatethe target word line 210 (e.g., applying a voltage to the word line210), to access a row including the target memory cell 205. The localmemory controller 260 may apply a specific signal (e.g., voltage) to thedigit line 215 during the write operation to store a specific state(e.g., charge) in the capacitor 230 of the memory cell 205, the specificstate (e.g., charge) may be indicative of a desired logic state.

In some cases, the local memory controller 260 may be configured toperform a read operation (e.g., a sense operation) on one or more memorycells 205 of the memory sub-array 200. During a read operation, thelogic state stored in a memory cell 205 of the memory sub-array 200 maybe determined. In some cases, a plurality of memory cells 205 may besensed during a single read operation. The local memory controller 260may identify a target memory cell 205 on which to perform the readoperation. The local memory controller 260 may identify a target wordline 210 and a target digit line 215 in electronic communication withthe target memory cell 205 (e.g., the address of the target memory cell205). The local memory controller 260 may activate the target word line210 (e.g., applying a voltage to the word line 210), to access a rowincluding the target memory cell 205. The target memory cell 205 maytransfer a signal to the sense component 245 in response to biasing theaccess lines. The sense component 245 may amplify the signal. The localmemory controller 260 may fire the sense component 245 (e.g., latch thesense component) and thereby compare the signal received from the memorycell 205 to the reference signal 250. Based on that comparison, thesense component 245 may determine a logic state that is stored on thememory cell 205. The local memory controller 260 may communicate thelogic state stored on the memory cell 205 to the external memorycontroller 105 (or the device memory controller 155) as part of the readoperation (e.g., by selecting data read from digit lines 215 usingcolumn decoder 225).

The row access logic 265 and the column access logic 275 may determine asubset of the array corresponding to the target memory cell 205. Thatis, the row access logic 265 and the column access logic 275 may beconfigured to determine the word line or lines 210 activated during theread operation and the digit line or lines 215 carrying the dataassociated with the read operation. The row access logic 265 and thecolumn access logic 275 may transmit an indication of the determinedsubset of the array (e.g., to a verifier as discussed herein). In someexamples, the indication of the subset of the array may indicate thesubset along one or more dimensions of the array. For example, theindication of the subset of the array may indicate the word line orlines 210 being activated during the read operation (e.g., a row MATindication). Additionally or alternatively, the indication of the subsetof the array may indicate the digit line or lines 215 selected duringthe read operation (e.g., a column MAT indication).

In some memory architectures, accessing the memory cell 205 may degradeor destroy the logic state stored in a memory cell 205. For example, aread operation performed in DRAM architectures may partially orcompletely discharge the capacitor of the target memory cell. The localmemory controller 260 may perform a re-write operation or a refreshoperation to return the memory cell to its original logic state. Thelocal memory controller 260 may re-write the logic state to the targetmemory cell after a read operation. In some cases, the re-writeoperation may be considered part of the read operation. Additionally,activating a single access line, such as a word line 210, may disturbthe state stored in some memory cells in electronic communication withthat access line. Thus, a re-write operation or refresh operation may beperformed on one or more memory cells that may not have been accessed.

FIG. 3 illustrates an example of a system 300 that supports techniquesfor command block management. The system 300 may include one or morecomponents described herein with reference to FIGS. 1 and 2 . Forexample, the system 300 may include a host device 305, which may be anexample of the external memory controller 105 as described withreference to FIG. 1 and a memory device 310, which may be an example ofthe memory device 110, the memory dice 160, or the memory die 200 asdescribed with reference to FIGS. 1 and 2 . The memory device 310 mayinclude a memory array 370, which may be an example of the memory arrays170 as described with reference to FIG. 1 . The memory device 310 mayalso include valid command circuitry 325, gate 345, mode registers 380,and event log registers 335.

Host device 305 may send commands to memory device 310 via a channel320, which may be an example of a channel 115 or CA channel 186 asdiscussed with reference to FIG. 1 . The memory device 310 may receivethe commands at memory pins 315 which may, in some cases, be coupledwith an input buffer. The commands may include individual commands(e.g., individual read or write commands), or burst commands (multiplesequential commands). The command or commands may be transmitted fromthe memory pins 315 (or input buffers coupled with the memory pins 315)to the valid command circuitry 325 via bus 330. The command or commandsreceived from the host device 305 may be propagated through the validcommand circuitry 325 to the gate 345. In some cases, the valid commandcircuitry 325 may cause the gate 345 to propagate defined commands(e.g., commands that are known by the memory device 310) to the decoder360 and block commands (e.g., not propagating commands to the decoder360) that are not defined. In this way, the memory device 310 mayprevent undefined commands from being executed, thus increasing areliability of the memory device 310.

A defined command may be a command associated with a defined instruction(e.g., a read instruction, a write instruction, a refresh instruction,etc.) and/or a defined address (e.g., row address, column address). Insome cases, there may be one or more possible commands that may not bedefined for the memory device 310. For example, a command may beindicated by three bits (e.g., received via three memory pins 315) suchthat there may be eight different possible bit combinations that thememory device 310 may receive. However, the memory device 310 may havejust five defined commands (e.g., five of the eight combinations aredefined, each corresponding to one of five distinct instructions). Thatis, there may be three possible received commands that may not beassociated with a defined instruction. In some cases, a number ofdefined addresses (e.g., addresses corresponding to a location of thememory array 370) may be based on the size of the memory array 370.These numbers are exemplary and for illustrative clarity only, and it isto be understand that a command may be indicated by any number of bitsand received over any number of pins, including via any order ofsignaling (e.g., binary or non-binary signaling).

The valid command circuitry 325 may determine whether a received commandis included in a set of commands that are defined for the memory device310. The memory device 310 may store a set of defined commands. In afirst example, the set of defined commands may be a preconfigured setthat is fixed by a vendor (e.g., during assembly) such as a DRAM vendor.The preconfigured set of defined commands may be non-programmable (e.g.,hard-wired or stored in Read Only Memory (ROM)) or one-time-programmable(OTP) (e.g., stored in one or more fuses or anti-fuses or one or morememory OTP memory). In a second example, the set of defined commands mayprogrammable after assembly (e.g., by the host 305, by the originalequipment manufacturer). In this example, the memory device 310 mayreceive the set of valid commands from the host device 305 and may storethe set of valid commands in a memory (e.g., register, volatile memory,or non-volatile memory). The valid command circuitry 325 may utilizecircuitry (e.g., a look-up table (LUT), a simplified processor circuitryimplementing a logic function) to determine whether the received commandis within the set of defined commands. In some cases, the valid commandcircuitry 325 may determine whether a sequence of commands is part of adefined set of command sequences.

The valid command circuitry 325 may transmit a pass/block signal 355 tothe gate 345 based on whether the command received from the host 305 iswithin the defined set of commands. For example, the valid commandcircuitry 325 may set the pass/block signal 355 to a first logic stateto signal the gate 345 to propagate the command and may set thepass/block signal 355 to a second logic state to signal the gate 345 toblock the command. The gate 345 may be a combination of logical gates orpass gates. For example, the gate 345 may set an instruction of internalcommand bus 365 to an instruction of the received command 330 when itidentifies the first logic state on the pass or block signal 355 and toa no-operation (NOP) instruction when it identifies the second logicstate on the pass or block signal 355.

In some cases, the valid command circuitry 325 may be different thandecoder 360. For example, decoder 360 may be a custom logic ortransistor level circuit, while valid command circuitry 325 may be asynthesized logic block (e.g., synthesized from a hardware descriptionlanguage). In some cases, the decoder 360 may use switched logic gateswhile valid command circuitry 325 uses static combinatorial logic gates.In some cases, the decoder 360 may map virtual addresses to physicaladdresses within memory array 370, while valid command circuitry 325 maydetermine if the virtual addresses are within a valid range ofaddresses, but may not map the addresses to physical addresses of memoryarray 370.

The valid command circuitry 325 may transmit an indication of an invalidcommand 340 (e.g., a command that is not included within a set ofdefined commands) to the event log registers 335. The event logregisters 335 may store the indication of the invalid command 340. Insome cases, the event log registers 335 may further store the invalidcommand itself. In the event that the memory device 310 receives asequence of commands from the host device 305, the event log registers335 may store each of the commands of the sequence of commands that isinvalid. In some instances, the valid command circuitry 325 may transmitthe indication of the invalid command 340 to the mode registers 380.

The event log registers 335 may record a number of invalid commandsreceived from the host device 305. For example, the event log registers335 may include a counting register for storing a number of invalidcommands. Here, the counting register may increment a stored value whenthe event log registers 335 receive the indication of the invalidcommand 340 from the valid command circuitry 325. In some cases, thenumber of recorded invalid commands may be based on a number of invalidcommands indicated by the valid command circuitry 325 within a giventime frame. The number of recorded invalid commands may be compared to athreshold. In some cases, if the number of recorded invalid commandssatisfies the threshold (e.g., the number of recorded invalid commandsis greater than or equal to the threshold), the event log register 335may transmit an indication of the satisfied threshold to the moderegisters 380 via bus 385. The memory device 310 may utilize thethreshold to determine a potential malicious attack. That is, when thethreshold is met, the memory device 310 may determine that the number ofinvalid commands may be associated with a malicious attack. Thethreshold may be preconfigured (e.g., set during assembly) orprogrammable (e.g., programmable by a host device 305). The thresholdmay be one command (e.g., a single invalid command may trigger theindication of the satisfied threshold), or multiple invalid commands, insome cases.

The mode registers 380 may indicate a mode of operation for the memorydevice 310. That is, the memory device 310 may operate according tomodes of operation, which may include an access mode and a safe mode. Inthe access mode, the memory device 310 may execute commands (e.g., thedefined commands) received from host device 305 at the indicated portionof memory array 370. However, during the safe mode, the memory device310 may apply a restriction of access to at least a portion of thememory array 370. For example, in the safe mode the memory device 310may block commands to one or more portions (e.g., rows, columns,sub-arrays, banks, bank groups) of the memory array 370 subject to therestriction of access. In some other examples, the memory device 310 maynot execute any defined commands during the safe mode. In some otherexamples, the memory device 310 may not execute certain types of definedcommands during the safe mode (e.g., the memory device 310 may executeread commands during a safe mode, but may not execute other types ofcommands). In some other examples, the memory device 310 may refreshsome (e.g., certain rows, sub-arrays, banks, bank groups) or all of thememory array 370 during the safe mode (e.g., autonomously orautomatically). In some instances, the mode registers 380 may indicatethe safe mode based on receiving the indication that the number ofrecorded invalid commands satisfies the threshold (e.g., from the eventlog registers 335). In some other instances, the mode registers 380 mayindicate the safe mode based on receiving the indication of the invalidcommand 340 from the valid command circuitry 325. For example, the moderegisters 380 may set a safe mode register to a logic ‘1’ indicating thesafe mode. During the safe mode, the memory device 310 may operate theportion of the memory array associated with the safe mode (e.g., therows, sub-arrays, bank(s), or bank groups operating according to thesafe mode) in a self-refresh mode.

The memory device 310 may maintain the safe mode for a predeterminedperiod of time (e.g., time period or number of clocks), or untilreceiving a command from the host device 305 to return to the accessmode. The command may indicate a reset procedure, which may transitionthe memory device 310 from the safe mode to the access mode. The commandto reset to the access mode may include a single command, or a sequenceof commands that may be known by host device 305 and by the memorydevice 310. The sequence may act as a guard key. Here, host device 305may transmit the sequence of commands (e.g., guard key) to memory device310. The memory device 310 (e.g., at the decoder 360 or valid commandcircuitry 325) may recognize the sequence of commands and transition theportion of the memory array 370 from the safe mode to the access mode.

The event log registers 335 may provide a feedback to the host device305 related to the invalid command. In some cases, the feedback mayinclude an indication of the invalid command. Additionally oralternatively, the feedback may include the invalid command received atthe memory pins 315. For example, the memory device 310 may include theinvalid command in the feedback in response to the host device 305transmitting a request to the memory device 305 for an indication of theinvalid command received at the memory pins 315. In another example, thefeedback may include an indication that the threshold has been satisfied(e.g., an indication that the memory device 310 is operating accordingto a safe mode).

The memory device 310 may send the feedback to the host device 305 viapath 395. In some cases, path 395 may include a distinct set of feedbackpins or sideband pins (e.g., separate from memory pins 315). In someother cases, path 395 may include the memory pins 315. For example, theindication of the invalid command may be sent by the same path (e.g.,including channel 320 and memory pins 315) as the host 305 uses toindicate commands to the memory device 310. When the memory device 310sends the feedback to the host device via pins (e.g., via feedback pins,via memory pins 315), a first pin may indicate an invalid command whileone or more other pins may transmit the received invalid command. Insome other cases, the host device 305 may poll one or more of the eventlog registers 335. For example, the host device 305 may poll a registerthat indicates that the memory device 310 received an invalid command.In another example, the host device 305 may poll a register (e.g., acounting register) to determine a number of invalid commands that thememory device 310 has received within a time window.

The host device 305 may respond to the received feedback. In some cases,the host device 305 may determine to transmit one or more commands basedon the feedback relating to the invalid command. For example, thefeedback may indicate that the memory device 310 has entered into a safemode of operation. Here, the host device 305 may transmit a command orcommands as part of a reset procedure to transition the memory device310 from the safe mode to the access mode. In another example, the hostdevice 305 may determine that a desired command was not executed (e.g.,due to the command not being defined at the memory device 310) anddetermine to re-transmit the same command, or transmit a differentcommand or command sequence for execution. Additionally oralternatively, the host device 305 may transmit a command sequence tothe memory device 310 to add a command to the set of defined commands.For example, the host device 305 may transmit a command sequence to addthe desired command to the set of defined commands at the memory device310.

In the case that the received command is defined at the memory device305, the valid command circuitry may determine that a received commandis included in the set of defined commands. Here, the valid commandcircuitry 325 may indicate via the pass/block signal 355 for the gate345 to propagate the received command as internal command 365 to thedecoder 360. The decoder 360 may receive the internal command 365 anddetermine an instruction and an address associated with the definedcommand. After decoding the command, the decoder 360 may subsequentlyindicate the instruction and the address to the memory array 370 (e.g.,via the bus 375). The address sent to the memory array 370 may be, forexample, a physical address of the memory array 370 including row,column, sub-array, bank, or bank group for the instruction (e.g., rowmatrix (MAT) and/or column MAT). In some cases, the mode registers 380may further indicate a portion of the memory array associated with thesafe mode of operation. In some other cases, the mode registers 380 mayindicate a type of command that is restricted during the safe mode ofoperation.

The memory array 370 may determine a mode of operation for the memorydevice 310 by polling one or more mode registers 380. The mode registers380 may indicate the mode of operation to the memory array 370 via bus390. For example, the memory array 370 may read a value stored at themode registers 380 to determine whether the memory device 310 isoperating according to an access mode or a safe mode. Additionally oralternatively, the decoder 360 may poll the mode registers to determinethe mode of operation for the memory device 310. Here, the decoder 360may adjust the instruction and/or the address sent to the memory array370 based on the determined mode of operation. For example, the decodermay not transmit, to the memory array 370, the instruction and addressif the instruction and/or address are restricted as part of the safemode of operation. Alternatively, the valid command circuitry 325 maypoll the mode registers 380 to determine whether a received command isexecutable in light of a current mode of operation. Here, the validcommand circuitry 325 may not propagate commands that are restricted aspart of the safe mode of operation.

If the memory device 310 is operating according to an access mode, thememory array 370 may access the indicated address and according to theindicated instruction (e.g., an instruction corresponding to a readinstruction, a refresh instruction, a write instruction). If the memorydevice 310 is operating according to a safe mode, the valid commandcircuitry 325, the decoder 360, or the memory array 310 may determine ifthe indicated address corresponds to a portion of the memory array 370that is associated with a restriction of access. If the indicatedaddress does correspond to the portion of the memory array 370 that isoperating within the restricted access mode, the defined command may notbe executed. If the indicated address does not correspond to the portionof the memory array 370 that is associated with a restriction of access,the defined command may be executed. Additionally or alternatively, ifthe memory device 310 is operating according to a safe mode, the memoryarray 310 may determine if the indicated instruction corresponds to aninstruction restricted by the safe mode of operation. If the indicatedinstruction does correspond to a restricted instruction, the definedcommand may not be executed. If the indicated instruction does notcorrespond to a restricted instruction, the defined command may beexecuted.

FIG. 4 shows an example diagram of a process flow 400 that supportstechniques for command block management. The features of process flow400 may be implemented or performed by a memory device (e.g., the memorydevice 110, the memory dice 160, the memory die 200, or the memorydevice 310 described with reference to FIGS. 1 through 3 ) or acomponent of a memory device such as the device memory controller 155,the local memory controllers 165, the local memory controller 260, asdescribed with reference to FIGS. 1 and 2 .

At block 405, circuitry associated with a memory device may receive acommand from a host device. The circuitry may correspond to, forexample, portions of the memory device 310 such as the memory pins 315and a corresponding input buffer, valid command circuitry 325, gate 345,decoder 360, or registers of FIG. 3 . In some cases, the memory devicemay be operating according to an access mode at 405 (e.g., the memorydevice may execute each valid command received from a host device).

At block 410, the circuitry may determine whether the received commandis valid. A valid command may correspond to a command included in a setof defined commands. The circuitry may compare the received command withthe set of defined commands. In the case that the received command isincluded in the set of defined commands (e.g., the command is valid),the circuitry may proceed to block 435. At block 435, the circuitry mayexecute the command according to an instruction and address indicated bythe command. Then, the circuitry may continue to operate in an accessmode (e.g., at block 440). Alternatively, when the circuitry determinesthat the received command is absent from the set of defined commands atblock 40 (e.g., the command is invalid), the circuitry may proceed toblock 415.

At block 415, the circuitry may block the command. For example, thecircuitry may prevent the command from being sent to a decoder (e.g., tobe decoded into an instruction and an address and subsequently executedat a memory array associated with the memory device). In some cases, thecircuitry may block the command by transmitting a block signal to a gate(e.g., as discussed with reference to FIG. 3 ). The block signal may actas a deactivation signal for the gate, or may set the gate to propagatea known command (e.g., NOP) to the decoder thus preventing the circuitryfrom transmitting the invalid command to a decoder. After the circuitryblocks the command, the circuitry may proceed to either block 420, 425,and/or 440.

At block 420, the circuitry may transmit a notification regarding theinvalid command to a host device (e.g., host device 305 as discussedwith reference to FIG. 3 ). The notification may include an indicationthat an invalid command was received (and subsequently blocked). Inanother example, the notification may include the received command thatwas blocked. Additionally or alternatively, the notification may includean indication that a threshold was satisfied. The threshold maycorrespond to a number of invalid commands (e.g., received within aconfigured time window) that may be indicative of a malicious attack.Therefore, the notification may indicate that the threshold has been met(e.g., the number of invalid commands received during the configuredtime window satisfied the threshold). In some other cases, thenotification may include the mode of operation of the memory device(e.g., an access mode, a safe mode) or a restriction associated with themode of operation (e.g., a bank or sub-array that is restricted). Afterthe circuitry transmits the notification to the host device, thecircuitry may proceed to either block 440 (e.g., operating according tothe access mode operation) or to block 425.

At 425, the circuitry may optionally transition the memory device froman access mode to a safe mode operation. In some cases, the circuitrymay transition the memory device to a safe mode operation in the eventthat the circuitry detects that the threshold number of invalid commandshas been met. That is, the circuitry may detect a potentially maliciousattack to the memory device and may switch to a safe mode operation torestrict the operation of the memory device (e.g., limit theinstructions to certain types of command, limit the portion/banks of amemory array for executing commands). After the circuitry transitionsthe memory device to a safe mode operation, the circuitry may proceed toblock 430.

At block 430, the circuitry may identify whether a reset procedure hasbeen executed. The reset procedure may be specific to the portions ofthe memory array that have been transitioned to a safe mode operation. Areset procedure may transition the memory array (or portions of thememory array) from the safe mode to the access mode. When the circuitrydetermines that the reset procedure has been executed, the circuitry mayproceed to block 440, where the circuitry may transition the memorydevice (or portions of the memory device that had been operatingaccording to the safe mode) into the access mode. Alternatively, whenthe circuitry determines that the reset procedure has not been executed,the circuitry may proceed to block 425 (e.g., the circuitry may continueto block certain types of access commands or the portion(s) of thememory array that are operating according to a safe mode).

FIG. 5 illustrates an example of a process flow 500 that supportstechniques for command block management. In some examples, process flow500 may be implemented by aspects of the systems 100 and 300, memory die200, and process flow 400. The process flow 500 may include operationsperformed by a host device 505, which may be an example of the hostdevice described with reference to FIGS. 1, 3, and 4 . The memory device510 may be an example of a memory device (e.g., the memory device 110,the memory dice 160, the memory die 200, or the memory device 310) asdescribed with reference to FIGS. 1 through 4 .

At 515, the memory device 510, comprising a memory array, may receive acommand from the host device 505. In some cases, the command may includean instruction and an address.

At 520, the memory device 510 may identify a set of valid commands forthe memory device 510. In some cases, the set of valid commands may bepreconfigured in the memory device 510. In some other cases, the set ofvalid commands may be programmable. Here, the memory device 510 mayreceive, from the host device 505, a signal indicating the set of validcommands.

At 525, the memory device 510 may determine that the command (e.g.,received at 515) is absent from the set of valid commands (e.g., thecommand is invalid). In some cases, the memory device 510 may determinethe validity of the command by comparing the command to a set of validcommands.

At 530, the memory device 510 may block, based at least in part ondetermining that the command is absent from the set of valid commands,the command from being decoded for execution by the memory device.

At 535, the memory device 510 may optionally switch from an access modeof operation (e.g., a first mode of operation) of the memory device 510to a safe mode of operation (e.g., a second mode of operation) of thememory device 510 based at least in part on determining that the commandis absent from the set of valid commands. In some cases, the memorydevice 510 may restrict access to at least one address of the memoryarray based at least in part on switching to the safe mode of operation.In some cases, the memory device 510 may operate at least one bank ofthe memory in a self-refresh mode based at least in part on switching tothe safe mode of operation. Additionally or alternatively, the memorydevice 510 may restrict the execution for at least one command of theset of valid commands based at least in part on switching to the safemode of operation (e.g., the execution of write commands may berestricted).

In the case that memory device switches to operating according to a safemode at 535, the memory device may subsequently receive, from the hostdevice 505 while operating in the safe mode, a command sequence forresetting the memory device 510 to the access mode (not shown). Thememory device 510 may switch from the safe mode to the access mode basedat least in part on receiving the command sequence.

At 540, the memory device 510 may optionally transmit, to the hostdevice 505, an indication that the command is absent from the set ofvalid commands (e.g., indicate that the command is invalid). In somecases, the memory device 510 may transmit the indication based at leastin part on a quantity of commands determined to be invalid satisfying athreshold. The memory device 510 may determine the threshold based onreceiving a signal indicating the threshold from the host device 505.

FIG. 6 illustrates an example of a process flow 600 that supportstechniques for command block management. In some examples, process flow600 may be implemented by aspects of the systems 100 and 300, memory die200, and process flows 400 and 500. The process flow 600 may includeoperations performed by a host device 605, which may be an example ofthe host device described with reference to FIGS. 1, 3, 4, and 5 . Theprocess flow 600 may include operations performed by a memory device610, which may be an example of a memory device (e.g., the memory device110, the memory dice 160, the memory die 200, the memory device 310, orthe memory device 510) as described with reference to FIGS. 1 through 5.

At 615, the memory device 610 may receive a plurality of commands (e.g.,in contiguous or non-contiguous clock cycles) from a host device 605.Each of the plurality of commands may include an instruction and/oraddress (e.g., row address, column address).

At 620, the memory device 610 may determine whether each command of theplurality of commands is included in a set of defined commands. In somecases, the memory device 610 may store the set of defined commands atthe memory device 610. Here, the memory device 610 may determine whethereach command is included in the set of defined commands by comparingeach of the plurality of commands to the stored set of defined commands.

At 625, the memory device 610 may decode a first command of theplurality of commands for execution on a memory array of the memorydevice 610 based at least in part on determining that the first commandis included in the set of defined commands (e.g., the first command maybe defined).

At 630, the memory device 610 may block a second command of theplurality of commands from being decoded for execution on the memoryarray based at least in part on determining that the second command isabsent from the set of defined commands (e.g., the command may beundefined).

At 635, the memory device 610 may, in some cases, determine a quantityof commands of the plurality of commands that are absent from the set ofdefined commands. That is, the memory device 610 may determine a numberof commands that are undefined. In some cases, the memory device 610 maycompare the quantity to a threshold. In some examples, the memory device610 may store one or more commands of the plurality of commands based atleast in part on determining that the one or more commands are absentfrom the set of defined commands.

At 640, the memory device 610 may switch from a first mode of operation(e.g., an access mode) of the memory device 610 to a second mode ofoperation (e.g., a safe mode) of the memory device 610 based ondetermining that the quantity satisfies the threshold. That is, thememory device 610 may switch to a safe mode in the event that a numberof undefined commands satisfies the threshold. In some cases, the memorydevice 610 may determine the threshold by receiving, from the hostdevice 605, a signal indicating the threshold.

At 645, the memory device 610 may transmit, to the host device 605, anindication that the quantity satisfies the threshold.

FIG. 7 illustrates an example of a process flow 700 that supportstechniques for command block management. In some examples, process flow700 may be implemented by aspects of the systems 100 and 300, memory die200, and process flows 400, 500, and 600. The process flow 700 mayinclude operations performed by a host device 705, which may be anexample of the host device described with reference to FIGS. 1, 3, 4, 5,and 6 . The process flow 700 may include operations performed by amemory device 710, which may be an example of a memory device (e.g., thememory device 110, the memory dice 160, the memory die 200, the memorydevice 310, the memory device 510, or the memory device 610) asdescribed with reference to FIGS. 1 through 6 .

At 715, the host device 705 may transmit, to the memory device 710, acommand for an operation on a memory array of the memory device 710. Thecommand may include an instruction and/or address (e.g., row address,column address).

At 720, the host device 705 may receive, from the memory device 710 inresponse to the command, an indication that the command as received atthe memory device 710 is absent from a set of valid commands for thememory device 710 (e.g., the command is invalid for the memory device710). In some cases, the indication may further include an indicationthat the memory device 710 may have switched from a first mode ofoperation (e.g., an access mode of operation) to a second mode ofoperation (e.g., a safe mode of operation) based on the command.

At 725, the host device 705 may process a second command from the memorydevice based on the indication. In some cases, processing a secondcommand may include the host device 705 modifying commands that arewaiting to be sent to the memory device 710. For example, the hostdevice 705 may change commands that are indicated as invalid by thememory device 710. In another example, the host device 705 may modifycommands that may not be executed by the memory device 710 according tothe second mode of operation. In another case, processing a secondcommand may include the host device 705 determining to retransmit thefirst command.

At 730, the host device 705 may transmit, to the memory device 710, asecond command. In some cases, the second command may be part of acommand sequence. In a first example, memory device 710 may be operatingin a second mode (e.g., a safe mode as indicated at 720). Here, the hostdevice 705 may transmit, to the memory device 710 while the memorydevice 710 is operating in the second mode, a command sequence forresetting the memory device 710 to the first mode. In a second example,the host device 705 may transmit, to the memory device 710, a commandsequence for adding the command to the set valid commands. In a thirdexample, the host device 705 may transmit, to the memory device 710, arequest for a representation of the command as received by the memorydevice 710. Here, the host device 705 may receive, from the memorydevice 710, an indication of the representation of the command.

FIG. 8 shows a block diagram 800 of a device 805 that supports commandblock management as disclosed herein. The device 805 may be an exampleof aspects of a memory device such as memory device 110, memory device310, memory device 510, memory device 610, or memory device 710 asdisclosed herein with reference to FIGS. 1, 3, 5, 6, and 7 . The device805 may include command receiver 810, a valid command set manager 815, acommand validation manager 820, a command blocker 825, an operation modemanager 830, a feedback component 835, a threshold manager 840, and acommand execution manager 845. Each of these modules may communicate,directly or indirectly, with one another (e.g., via one or more buses).

The command receiver 810 may receive, at a memory device including amemory array, a command from a host device. In some cases, the commandincludes an instruction and an address.

The valid command set manager 815 may identify a set of valid commandsfor the memory device. In some examples, the valid command set manager815 may receive, from the host device, a signal indicating the set ofvalid commands. In some other examples, the set of valid commands ispreconfigured in the memory device.

The command validation manager 820 may determine that the command isabsent from the set of valid commands based on evaluating the commandand the set of valid commands.

The command blocker 825 may block, based on determining that the commandis absent from the set of valid commands, the command from being decodedfor execution by the memory device.

The operation mode manager 830 may switch from a first mode of operationof the memory device to a second mode of operation of the memory devicebased on determining that the command is absent from the set of validcommands. In some examples, the operation mode manager 830 may restrictaccess to at least one address of the memory array based on switching tothe second mode of operation. In some examples, the operation modemanager 830 may operate at least one bank of the memory array in aself-refresh mode based on switching to the second mode of operation. Insome other examples, the operation mode manager 830 may restrictexecution for at least one command of the set of valid commands based onswitching to the second mode of operation. In some examples, theoperation mode manager 830 may receive, from the host device whileoperating in the second mode, a command sequence for resetting thememory device to the first mode. In some examples, the operation modemanager 830 may switch the memory device from the second mode to thefirst mode based on receiving the command sequence.

In some examples, the feedback component 835 may transmit, to the hostdevice, an indication that the command is absent from the set of validcommands.

The command receiver 810 may receive, from a host device at a memorydevice including a memory array, a command for an operation by thememory device. The command validation manager 820 may determine avalidity of the command by comparing the command to a set of validcommands.

The feedback component 835 may transmit, to the host device, anindication of the validity of the command. In some examples, thefeedback component 835 may transmit the indication based on a quantityof commands determined to be invalid satisfying a threshold. In somecases, the threshold manager 840 may receive a signal indicating thethreshold from the host device.

The command receiver 810 may receive, at a memory device, a set ofcommands from a host device.

The command validation manager 820 may determine whether each command ofthe set of commands is included in a set of defined commands. In somecases, the command validation manager 820 may store one or more commandsof the set of commands based on determining that the one or morecommands are absent from the set of defined commands. In some examples,the command validation manager 820 may store the set of defined commandsat the memory device. In some examples, the command validation manager820 may determine a quantity of commands of the set of commands that areabsent from the set of defined commands.

The threshold manager 840 may receive, from the host device, a signalindicating the threshold. In some examples, the threshold manager 840may compare the quantity to a threshold.

The operation mode manager 830 may switch from a first mode of operationof the memory device to a second mode of operation of the memory devicebased on determining that the quantity satisfies the threshold.

The feedback component 835 may transmit, to the host device, anindication that the quantity satisfies the threshold. In some examples,the feedback component 835 may transmit, to the host device, anindication of the one or more commands (e.g., the one or more commandsstored based on determining that the one or more commands are absentfrom the set of defined commands).

The command execution manager 845 may decode a first command of the setof commands for execution on a memory array of the memory device basedon determining that the first command is included in the set of definedcommands.

The command blocker 825 may block a second command of the set ofcommands from being decoded for execution on the memory array based ondetermining that the second command is absent from the set of definedcommands.

FIG. 9 shows a block diagram 900 of a device 905 that supports commandblock management as disclosed herein. The device 905 may be an exampleof aspects of a host device such as host device 305, host device 505,host device 605, or host device 705 as disclosed herein with referenceto FIGS. 3 and 5 through 7 . The device 905 may include a commandtransmitter 910, a feedback receiver 915, and a command processor 920.Each of these modules may communicate, directly or indirectly, with oneanother (e.g., via one or more buses).

The command transmitter 910 may transmit, to a memory device, a commandfor an operation on a memory array of the memory device. In someexamples, the command transmitter 910 may transmit, to the memorydevice, the second command. In some examples, the command transmitter910 may transmit, to the memory device while the memory device isoperating in the second mode, a command sequence for resetting thememory device to the first mode. In some cases, the command transmitter910 may transmit, to the memory device, a command sequence that includesthe second command, the command sequence for adding the command to theset of valid commands. In some instances, the command transmitter 910may transmit, to the memory device, a request for a representation ofthe command as received by the memory device.

The feedback receiver 915 may receive, from the memory device inresponse to the command, an indication that the command as received atthe memory device is absent from a set of valid commands for the memorydevice. In some examples, the feedback receiver 915 may receive, fromthe memory device, an indication that the memory device has switchedfrom a first mode of operation to a second mode of operation based onthe command. In some instances, the feedback receiver 915 may receive,from the memory device, an indication of the representation of thecommand.

The command processor 920 may process a second command for the memorydevice based on the indication.

FIG. 10 shows a flowchart illustrating a method 1000 that supportssystems, devices, and methods for command block management as disclosedherein. The operations of method 1000 may be implemented by a memorydevice (e.g., memory device 110, memory device 310, memory device 510,memory device 610, or memory device 710 as disclosed herein withreference to FIGS. 1, 3, 5, 6, and 7 ) or its components as describedherein. In some examples, a memory device may execute a set ofinstructions to control the functional elements of the memory device toperform the functions described herein. Additionally or alternatively, amemory device may perform aspects of the functions described below usingspecial-purpose hardware.

At 1005, the memory device may receive, at a memory device including amemory array, a command from a host device. The operations of 1005 maybe performed according to the methods described herein. In someexamples, aspects of the operations of 1005 may be performed by acommand receiver as described with reference to FIG. 8 .

At 1010, the memory device may identify a set of valid commands for thememory device. The operations of 1010 may be performed according to themethods described herein. In some examples, aspects of the operations of1010 may be performed by a valid command set manager as described withreference to FIG. 8 .

At 1015, the memory device may determine that the command is absent fromthe set of valid commands based on evaluating the command and the set ofvalid commands. The operations of 1015 may be performed according to themethods described herein. In some examples, aspects of the operations of1015 may be performed by a command validation manager as described withreference to FIG. 8 .

At 1020, the memory device may block, based on determining that thecommand is absent from the set of valid commands, the command from beingdecoded for execution by the memory device. The operations of 1020 maybe performed according to the methods described herein. In someexamples, aspects of the operations of 1020 may be performed by acommand blocker as described with reference to FIG. 8 .

An apparatus for performing a method or methods, such as the method1000, is described. The apparatus may include means for means forreceiving, at a memory device including a memory array, a command from ahost device, identifying a set of valid commands for the memory device,determining that the command is absent from the set of valid commandsbased on evaluating the command and the set of valid commands, andblocking, based on determining that the command is absent from the setof valid commands, the command from being decoded for execution by thememory device.

In some examples, the apparatus may include features for switching froma first mode of operation of the memory device to a second mode ofoperation of the memory device based on determining that the command maybe absent from the set of valid commands.

In some cases, the apparatus may include features for restricting accessto at least one address of the memory array based on switching to thesecond mode of operation.

In some instances, the apparatus may include features for operating atleast one bank of the memory array in a self-refresh mode based onswitching to the second mode of operation.

In some examples, the apparatus may include features for restrictingexecution for at least one command of the set of valid commands based onswitching to the second mode of operation.

In some cases, the apparatus may include features for receiving, fromthe host device while operating in the second mode, a command sequencefor resetting the memory device to the first mode, and switching thememory device from the second mode to the first mode based on receivingthe command sequence.

In some instances, the apparatus may include features for transmitting,to the host device, an indication that the command may be absent fromthe set of valid commands.

In some examples, the apparatus may include features for receiving, fromthe host device, a signal indicating the set of valid commands.

FIG. 11 shows a flowchart illustrating a method 1100 that supportssystems, devices, and methods for command block management as disclosedherein. The operations of method 1100 may be implemented by a memorydevice (e.g., memory device 110, memory device 310, memory device 510,memory device 610, or memory device 710 as disclosed herein withreference to FIGS. 1, 3, 5, 6, and 7 ) or its components as describedherein. In some examples, a memory device may execute a set ofinstructions to control the functional elements of the memory device toperform the functions described herein. Additionally or alternatively, amemory device may perform aspects of the functions described hereinusing special-purpose hardware.

At 1105, the memory device including a memory array may receive acommand from a host device. The operations of 1105 may be performedaccording to the methods described herein. In some examples, aspects ofthe operations of 1105 may be performed by a command receiver asdescribed with reference to FIG. 8 .

At 1110, the memory device may identify a set of valid commands for thememory device. The operations of 1110 may be performed according to themethods described herein. In some examples, aspects of the operations of1110 may be performed by a valid command set manager as described withreference to FIG. 8 .

At 1115, the memory device may determine that the command is absent fromthe set of valid commands based on evaluating the command and the set ofvalid commands. The operations of 1115 may be performed according to themethods described herein. In some examples, aspects of the operations of1115 may be performed by a command validation manager as described withreference to FIG. 8 .

At 1120, the memory device may block, based on determining that thecommand is absent from the set of valid commands, the command from beingdecoded for execution by the memory device. The operations of 1120 maybe performed according to the methods described herein. In someexamples, aspects of the operations of 1120 may be performed by acommand blocker as described with reference to FIG. 8 .

At 1125, the memory device may switch from a first mode of operation ofthe memory device to a second mode of operation of the memory devicebased on determining that the command is absent from the set of validcommands. The operations of 1125 may be performed according to themethods described herein. In some examples, aspects of the operations of1125 may be performed by an operation mode manager as described withreference to FIG. 8 .

At 1130, the memory device may transmit, to the host device, anindication that the command is absent from the set of valid commands.The operations of 1130 may be performed according to the methodsdescribed herein. In some examples, aspects of the operations of 1130may be performed by a feedback component as described with reference toFIG. 8 .

FIG. 12 shows a flowchart illustrating a method 1200 that supportssystems, devices, and methods for command block management as disclosedherein. The operations of method 1200 may be implemented by a memorydevice (e.g., memory device 110, memory device 310, memory device 510,memory device 610, or memory device 710 as disclosed herein withreference to FIGS. 1, 3, 5, 6, and 7 ) or its components as describedherein. In some examples, a memory device may execute a set ofinstructions to control the functional elements of the memory device toperform the functions described herein. Additionally or alternatively, amemory device may perform aspects of the functions described hereinusing special-purpose hardware.

At 1205, the memory device may receive, from a host device at a memorydevice including a memory array, a command for an operation by thememory device. The operations of 1205 may be performed according to themethods described herein. In some examples, aspects of the operations of1205 may be performed by a command receiver as described with referenceto FIG. 8 .

At 1210, the memory device may determine a validity of the command bycomparing the command to a set of valid commands. The operations of 1210may be performed according to the methods described herein. In someexamples, aspects of the operations of 1210 may be performed by acommand validation manager as described with reference to FIG. 8 .

At 1215, the memory device may transmit, to the host device, anindication of the validity of the command. The operations of 1215 may beperformed according to the methods described herein. In some examples,aspects of the operations of 1215 may be performed by a feedbackcomponent as described with reference to FIG. 8 .

An apparatus for performing a method or methods, such as the method1200, is described. The apparatus may include means for receiving, froma host device at a memory device including a memory array, a command foran operation by the memory device, determining a validity of the commandby comparing the command to a set of valid commands, and transmitting,to the host device, an indication of the validity of the command.

In some examples, the apparatus may include features for transmittingthe indication based on a quantity of commands determined to be invalidsatisfying a threshold.

In some cases, the apparatus may include features for receiving a signalindicating the threshold from the host device.

FIG. 13 shows a flowchart illustrating a method 1300 that supportssystems, devices, and methods for command block management as disclosedherein. The operations of method 1300 may be implemented by a memorydevice (e.g., memory device 110, memory device 310, memory device 510,memory device 610, or memory device 710 as disclosed herein withreference to FIGS. 1, 3, 5, 6, and 7 ) or its components as describedherein. In some examples, a memory device may execute a set ofinstructions to control the functional elements of the memory device toperform the functions described herein. Additionally or alternatively, amemory device may perform aspects of the functions described hereinusing special-purpose hardware.

At 1305, the memory device may receive, at a memory device, a set ofcommands from a host device. The operations of 1305 may be performedaccording to the methods described herein. In some examples, aspects ofthe operations of 1305 may be performed by a command receiver asdescribed with reference to FIG. 8 .

At 1310, the memory device may determine whether each command of the setof commands is included in a set of defined commands. The operations of1310 may be performed according to the methods described herein. In someexamples, aspects of the operations of 1310 may be performed by acommand validation manager as described with reference to FIG. 8 .

At 1315, the memory device may decode a first command of the set ofcommands for execution on a memory array of the memory device based ondetermining that the first command is included in the set of definedcommands. The operations of 1315 may be performed according to themethods described herein. In some examples, aspects of the operations of1315 may be performed by a command execution manager as described withreference to FIG. 8 .

At 1320, the memory device may block a second command of the set ofcommands from being decoded for execution on the memory array based ondetermining that the second command is absent from the set of definedcommands. The operations of 1320 may be performed according to themethods described herein. In some examples, aspects of the operations of1320 may be performed by a command blocker as described with referenceto FIG. 8 .

An apparatus for performing a method or methods, such as the method1300, is described. The apparatus may include means for receiving, at amemory device, a set of commands from a host device, determining whethereach command of the set of commands is included in a set of definedcommands, decoding a first command of the set of commands for executionon a memory array of the memory device based on determining that thefirst command is included in the set of defined commands, and blocking asecond command of the set of commands from being decoded for executionon the memory array based on determining that the second command isabsent from the set of defined commands.

In some examples, the apparatus may include features for determining aquantity of commands of the set of commands that may be absent from theset of defined commands, and comparing the quantity to a threshold.

In some cases, the apparatus may include features for switching from afirst mode of operation of the memory device to a second mode ofoperation of the memory device based on determining that the quantitysatisfies the threshold.

In some instances, the apparatus may include features for transmitting,to the host device, an indication that the quantity satisfies thethreshold.

In some examples, the apparatus may include features for storing one ormore commands of the set of commands based on determining that the oneor more commands may be absent from the set of defined commands, andtransmitting, to the host device, an indication of the one or morecommands.

In some aspects, the apparatus may include features for receiving, fromthe host device, a signal indicating the threshold.

In some cases, the apparatus may include features for storing the set ofdefined commands at the memory device.

FIG. 14 shows a flowchart illustrating a method 1400 that supportscommand block management as disclosed herein. The operations of method1400 may be implemented may be implemented by a host device (e.g., hostdevice 305, host device 505, host device 605, or host device 705 asdisclosed herein with reference to FIGS. 3 and 5 through 7 ) or itscomponents as described herein. In some examples, a host device mayexecute a set of instructions to control the functional elements of thehost device to perform the functions described herein. Additionally oralternatively, a host device may perform aspects of the functionsdescribed herein using special-purpose hardware.

At 1405, the host device may transmit, to a memory device, a command foran operation on a memory array of the memory device. The operations of1405 may be performed according to the methods described herein. In someexamples, aspects of the operations of 1405 may be performed by acommand transmitter as described with reference to FIG. 9 .

At 1410, the host device may receive, from the memory device in responseto the command, an indication that the command as received at the memorydevice is absent from a set of valid commands for the memory device. Theoperations of 1410 may be performed according to the methods describedherein. In some examples, aspects of the operations of 1410 may beperformed by a feedback receiver as described with reference to FIG. 9 .

At 1415, the host device may process a second command for the memorydevice based on the indication. The operations of 1415 may be performedaccording to the methods described herein. In some examples, aspects ofthe operations of 1415 may be performed by a command processor asdescribed with reference to FIG. 9 .

At 1420, the host device may transmit, to the memory device, the secondcommand. The operations of 1420 may be performed according to themethods described herein. In some examples, aspects of the operations of1420 may be performed by a command transmitter as described withreference to FIG. 9 .

An apparatus for performing a method or methods, such as the method1400, is described. The apparatus may include means for transmitting, toa memory device, a command for an operation on a memory array of thememory device, receiving, from the memory device in response to thecommand, an indication that the command as received at the memory deviceis absent from a set of valid commands for the memory device, processinga second command for the memory device based on the indication, andtransmitting, to the memory device, the second command.

In some examples, the apparatus may include features for receiving, fromthe memory device, an indication that the memory device may haveswitched from a first mode of operation to a second mode of operationbased on the command.

In some cases, the apparatus may include features for transmitting, tothe memory device while the memory device may be operating in the secondmode, a command sequence for resetting the memory device to the firstmode.

In some instances, the apparatus may include features for transmitting,to the memory device, a command sequence that includes the secondcommand, the command sequence for adding the command to the set of validcommands.

In some examples, the apparatus may include features for transmitting,to the memory device, a request for a representation of the command asreceived by the memory device, and receiving, from the memory device, anindication of the representation of the command.

It should be noted that the methods described above describe possibleimplementations, and that the operations and the steps may be rearrangedor otherwise modified and that other implementations are possible.Further, aspects from two or more of the methods may be combined.

In some examples, an apparatus for command block management may performaspects of the functions described herein using general- orspecial-purpose hardware. The apparatus may include a memory array of amemory device, circuitry operable to receive a set of commands from ahost device, a decoder coupled with the circuitry and the memory arrayand operable to decode commands received from the circuitry forexecution by the apparatus; and where the circuitry is operable topropagate a first command of the plurality of commands to the decoderbased on determining that the first command is included in a set ofvalid commands, and block a second command from being sent to thedecoder based on a determination that the second command is absent fromthe set of valid commands.

In some cases, the circuitry may be further operable to switch from afirst mode of operation of the memory device to a second mode ofoperation of the memory device based on determining that the secondcommand is absent from the set of valid commands.

In some instances, the circuitry may be further operable to switch fromthe first mode of operation to the second mode of operation based on aquantity of received commands that may be not included in the set ofvalid commands satisfying a threshold.

In some examples, the circuitry may be further operable to receive, fromthe host device while operating in the second mode, a command sequencefor resetting the memory device to the first mode, and switch the memorydevice from the second mode to the first mode based on receiving thecommand sequence.

In some cases, the circuitry may be further operable to transmit, to thehost device, an indication that the second command may be not includedin the set of valid commands.

In some instances, the circuitry may be further operable to transmit theindication based on a quantity of received commands that may be notincluded in the set of valid commands satisfying a threshold.

In some examples, the apparatus may include a buffer operable to storeone or more commands of the set of commands based on determining thatthe second command may be absent from the set of valid commands.

In some cases, the circuitry may be further operable to receive, fromthe host device, a signal indicating a request for a stored command ofthe set of commands, and transmit, to the host device, an indication ofthe stored command.

In some instances, each of the set of commands may be received via a setof instruction pins, and where the set of valid commands includes asubset of a command space of combinations of the set of instructionpins.

In some examples, each of the set of commands may be received via a setof instruction pins and a set of address pins, and where the set ofvalid commands includes a subset of a command space of combinations ofthe set of instruction pins and the set of address pins.

Although certain features may be described herein with respect to or inthe context of DRAM technology, this is for illustrative purposes only,and one of ordinary skill in the art will appreciate that the teachingsherein may be applied to any type of memory device. For example, theteachings herein may be applied to volatile or non-volatile memorydevices such as magnetic hard disks, random access memory (RAM),read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM(SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM(RRAM), flash memory, phase change memory (PCM), and others.

Information and signals described herein may be represented using any ofa variety of different technologies and techniques. For example, data,instructions, commands, information, signals, bits, symbols, and chipsthat may be referenced throughout the above description may berepresented by voltages, currents, electromagnetic waves, magneticfields or particles, optical fields or particles, or any combinationthereof. Some drawings may illustrate signals as a single signal;however, it will be understood by a person of ordinary skill in the artthat the signal may represent a bus of signals, where the bus may have avariety of bit widths.

As used herein, the term “virtual ground” refers to a node of anelectrical circuit that is held at a voltage of approximately zero volts(0V) but that is not directly coupled with ground. Accordingly, thevoltage of a virtual ground may temporarily fluctuate and return toapproximately 0V at steady state. A virtual ground may be implementedusing various electronic circuit elements, such as a voltage dividerconsisting of operational amplifiers and resistors. Otherimplementations are also possible. “Virtual grounding” or “virtuallygrounded” means connected to approximately 0V.

The terms “electronic communication,” “conductive contact,” “connected,”and “coupled” may refer to a relationship between components thatsupports the flow of signals between the components. Components areconsidered in electronic communication with (or in conductive contactwith or connected with or coupled with) one another if there is anyconductive path between the components that can, at any time, supportthe flow of signals between the components. At any given time, theconductive path between components that are in electronic communicationwith each other (or in conductive contact with or connected with orcoupled with) may be an open circuit or a closed circuit based on theoperation of the device that includes the connected components. Theconductive path between connected components may be a direct conductivepath between the components or the conductive path between connectedcomponents may be an indirect conductive path that may includeintermediate components, such as switches, transistors, or othercomponents. In some cases, the flow of signals between the connectedcomponents may be interrupted for a time, for example, using one or moreintermediate components such as switches or transistors.

The term “coupling” refers to condition of moving from an open-circuitrelationship between components in which signals are not presentlycapable of being communicated between the components over a conductivepath to a closed-circuit relationship between components in whichsignals are capable of being communicated between components over theconductive path. When a component, such as a controller, couples othercomponents together, the component initiates a change that allowssignals to flow between the other components over a conductive path thatpreviously did not permit signals to flow.

The term “isolated” refers to a relationship between components in whichsignals are not presently capable of flowing between the components.Components are isolated from each other if there is an open circuitbetween them. For example, two components separated by a switch that ispositioned between the components are isolated from each other when theswitch is open. When a controller isolates two components, thecontroller affects a change that prevents signals from flowing betweenthe components using a conductive path that previously permitted signalsto flow.

The devices discussed herein, including a memory array, may be formed ona semiconductor substrate, such as silicon, germanium, silicon-germaniumalloy, gallium arsenide, gallium nitride, etc. In some cases, thesubstrate is a semiconductor wafer. In other cases, the substrate may bea silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG)or silicon-on-sapphire (SOP), or epitaxial layers of semiconductormaterials on another substrate. The conductivity of the substrate, orsub-regions of the substrate, may be controlled through doping usingvarious chemical species including, but not limited to, phosphorous,boron, or arsenic. Doping may be performed during the initial formationor growth of the substrate, by ion-implantation, or by any other dopingmeans.

A switching component or a transistor discussed herein may represent afield-effect transistor (FET) and comprise a three terminal deviceincluding a source, drain, and gate. The terminals may be connected toother electronic elements through conductive materials, e.g., metals.The source and drain may be conductive and may comprise a heavily-doped,e.g., degenerate, semiconductor region. The source and drain may beseparated by a lightly-doped semiconductor region or channel. If thechannel is n-type (i.e., majority carriers are signals), then the FETmay be referred to as a n-type FET. If the channel is p-type (i.e.,majority carriers are holes), then the FET may be referred to as ap-type FET. The channel may be capped by an insulating gate oxide. Thechannel conductivity may be controlled by applying a voltage to thegate. For example, applying a positive voltage or negative voltage to ann-type FET or a p-type FET, respectively, may result in the channelbecoming conductive. A transistor may be “on” or “activated” when avoltage greater than or equal to the transistor's threshold voltage isapplied to the transistor gate. The transistor may be “off” or“deactivated” when a voltage less than the transistor's thresholdvoltage is applied to the transistor gate.

The description set forth herein, in connection with the appendeddrawings, describes example configurations and does not represent allthe examples that may be implemented or that are within the scope of theclaims. The term “exemplary” used herein means “serving as an example,instance, or illustration,” and not “preferred” or “advantageous overother examples.” The detailed description includes specific details toproviding an understanding of the described techniques. Thesetechniques, however, may be practiced without these specific details. Insome instances, well-known structures and devices are shown in blockdiagram form to avoid obscuring the concepts of the described examples.

In the appended figures, similar components or features may have thesame reference label. Further, various components of the same type maybe distinguished by following the reference label by a dash and a secondlabel that distinguishes among the similar components. If just the firstreference label is used in the specification, the description isapplicable to any one of the similar components having the same firstreference label irrespective of the second reference label.

Information and signals described herein may be represented using any ofa variety of different technologies and techniques. For example, data,instructions, commands, information, signals, bits, symbols, and chipsthat may be referenced throughout the above description may berepresented by voltages, currents, electromagnetic waves, magneticfields or particles, optical fields or particles, or any combinationthereof.

The various illustrative blocks and modules described in connection withthe disclosure herein may be implemented or performed with ageneral-purpose processor, a DSP, an ASIC, an FPGA or other programmablelogic device, discrete gate or transistor logic, discrete hardwarecomponents, or any combination thereof designed to perform the functionsdescribed herein. A general-purpose processor may be a microprocessor,but in the alternative, the processor may be any processor, controller,microcontroller, or state machine. A processor may also be implementedas a combination of computing devices (e.g., a combination of a DSP anda microprocessor, multiple microprocessors, one or more microprocessorsin conjunction with a DSP core, or any other such configuration).

The functions described herein may be implemented in hardware, softwareexecuted by a processor, firmware, or any combination thereof. Ifimplemented in software executed by a processor, the functions may bestored on or transmitted over as one or more instructions or code on acomputer-readable medium. Other examples and implementations are withinthe scope of the disclosure and appended claims. For example, due to thenature of software, functions described above can be implemented usingsoftware executed by a processor, hardware, firmware, hardwiring, orcombinations of any of these. Features implementing functions may alsobe physically located at various positions, including being distributedsuch that portions of functions are implemented at different physicallocations. Also, as used herein, including in the claims, “or” as usedin a list of items (for example, a list of items prefaced by a phrasesuch as “at least one of” or “one or more of”) indicates an inclusivelist such that, for example, a list of at least one of A, B, or C meansA or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, asused herein, the phrase “based on” shall not be construed as a referenceto a closed set of conditions. For example, an exemplary step that isdescribed as “based on condition A” may be based on both a condition Aand a condition B without departing from the scope of the presentdisclosure. In other words, as used herein, the phrase “based on” shallbe construed in the same manner as the phrase “based at least in parton.”

The description herein is provided to enable a person skilled in the artto make or use the disclosure. Various modifications to the disclosurewill be apparent to those skilled in the art, and the generic principlesdefined herein may be applied to other variations without departing fromthe scope of the disclosure. Thus, the disclosure is not limited to theexamples and designs described herein, but is to be accorded thebroadest scope consistent with the principles and novel featuresdisclosed herein.

What is claimed is:
 1. A method, comprising: receiving, at a memorydevice comprising a memory die, a command; determining that the commandis absent from a set of valid commands based at least in part onevaluating the command and the set of valid commands; setting a moderegister to a value indicating a safe mode of operation for the memorydevice, the safe mode allowing execution of a read command andrestricting execution of a write command; and blocking, based at leastin part on determining that the command is absent from the set of validcommands, the command from being decoded.
 2. The method of claim 1,further comprising: switching from a first mode of operation of thememory device to the safe mode of operation of the memory device basedat least in part on setting the mode register to the value.
 3. Themethod of claim 2, further comprising: restricting access to one or moreaddresses of the memory die.
 4. The method of claim 2, furthercomprising: operating one or more banks of the memory die in aself-refresh mode based at least in part on switching to the safe modeof operation.
 5. The method of claim 2, further comprising: restrictingexecution for one or more commands of the set of valid commands based atleast in part on switching to the safe mode of operation.
 6. The methodof claim 2, further comprising: receiving, while operating in the safemode, a command sequence for resetting the memory device to the firstmode; and switching the memory device from the safe mode to the firstmode based at least in part on receiving the command sequence.
 7. Themethod of claim 1, further comprising: transmitting an indication thatthe command is absent from the set of valid commands.
 8. A method,comprising: receiving, at a memory device comprising a memory die, aplurality of commands; determining whether each command of the pluralityof commands is included in a set of defined commands for a memory arrayof the memory die; decoding a first command of the plurality of commandsfor execution on the memory array of the memory die based at least inpart on determining that the first command is included in the set ofdefined commands; setting a mode register to a value based at least inpart on determining that a second command of the plurality of commandsis absent from the set of defined commands, the value indicating a safemode of operation for the memory device, the safe mode allowingexecution of a read command and restricting execution of a writecommand; and blocking the second command of the plurality of commandsfrom being decoded based at least in part on determining that the secondcommand is absent from the set of defined commands.
 9. The method ofclaim 8, further comprising: determining a quantity of commands of theplurality of commands that are absent from the set of defined commands;and comparing the quantity to a threshold.
 10. The method of claim 9,further comprising: switching from a first mode of operation of thememory device to the safe mode of operation of the memory device basedat least in part on determining that the quantity satisfies thethreshold.
 11. The method of claim 9, further comprising: transmittingan indication that the quantity satisfies the threshold.
 12. The methodof claim 9, further comprising: receiving a signal indicating thethreshold.
 13. The method of claim 8, further comprising: storing one ormore commands of the plurality of commands based at least in part ondetermining that the one or more commands are absent from the set ofdefined commands.
 14. The method of claim 8, further comprising: storingthe set of defined commands at the memory device.
 15. An apparatus,comprising: a memory array; circuitry operable to receive a command; anda decoder coupled with the circuitry and the memory array and operableto decode the command received from the circuitry for execution by theapparatus, wherein the apparatus is operable to: determine that thecommand is absent from a set of valid commands based at least in part onevaluating the command and the set of valid commands; set a moderegister to a value indicating a safe mode of operation for theapparatus, the safe mode allowing execution of a read command andrestricting execution of a write command; and block, based at least inpart on determining that the command is absent from the set of validcommands, the command from being decoded.
 16. The apparatus of claimError! Reference source not found., wherein the apparatus is operableto: switch from a first mode of operation of the apparatus to the safemode of operation of the apparatus based at least in part on setting themode register to the value.
 17. The apparatus of claim 16, wherein theapparatus is operable to: restrict access to one or more addresses ofthe memory array.
 18. The apparatus of claim 16, wherein the apparatusis operable to: operate one or more banks of the memory array in aself-refresh mode based at least in part on switching to the safe modeof operation.
 19. The apparatus of claim 16, wherein the apparatus isoperable to: restrict execution for one or more commands of the set ofvalid commands based at least in part on switching to the safe mode ofoperation.
 20. The apparatus of claim 16, wherein the apparatus isoperable to: receive, while operating in the safe mode, a commandsequence for resetting the apparatus to the first mode; and switch theapparatus from the safe mode to the first mode based at least in part onreceiving the command sequence.